Country for PR: United States
Contributor: PR Newswire New York
Thursday, March 18 2021 - 02:10
AsiaNet
Arasan announces its next generation of C-PHY / D-PHY Combo IP core compliant with the latest MIPI Specifications
SAN JOSE, Calif., Mar. 18, 2021 /PRNewswire-AsiaNet/--

  -- Arasan Chip Systems, a leading provider of semiconductor IP 
     for IoT, mobile and automobile SoCs, today announced the 
     immediate availability of its MIPI C/D-PHY Combo IP core compliant 
     with the MIPI C-PHY v2.0 and D-PHY 2.5 Specifications.

Arasan Chip Systems, a leading provider of semiconductor IP for mobile and 
automobile SoCs, today announces the immediate availability of its MIPI 
C-PHY(SM)/ D-PHY(SM) Combo IP which is compliant with the latest MIPI C-PHY(SM) 
v2.0 and MIPI D-PHY(SM) v2.5 specifications. The upgraded MIPI C-PHY(SM) / 
D-PHY(SM) Combo IP is seamlessly integrated with Arasan's own MIPI CSI-2(R) IP 
and MIPI DSI(R) IP as part of Arasan's Total IPTM for MIPI Imaging and Display 
Solutions. This 2nd generation of Arasan's MIPI C-PHY(SM)/D-PHY(SM) combo IP 
has been re-engineered for ultra low power consumption leveraging the 
advantages of the FINFET Technology. 

Logo - https://mma.prnewswire.com/media/1445207/Arasan_Total_IP_Logo.jpg

Arasan's MIPI C-PHY(SM) v2.0 / D-PHY(SM) v2.5 combo IP delivers 6 Gbps per lane 
for a max throughput of 24Gbps in D-PHY(SM) mode and 6Gsps per trio for a max 
throughput of 41Gbps in C-PHY(SM) mode. Other significant feature upgrades 
include:

     - When used with Arasan's  MIPI CSI-2 or MIPI DSI-2(R), the 
       MIPI C-PHY(SM)/D-PHY(SM) combo IP offers built-in test 
       capabilities including PRBS generator and internal loopback to 
       support cost effective tests for high volume manufacturing. 
     - New power saving HS-Tx half swing mode for D-PHY(SM), 
     - On-board programmable PLL with Spread Spectrum Clocking, with or 
       without deskew calibrations and equilizations for different 
       operating speeds of D-PHY(SM),Power management functions such as 
       reduced HS-TX swing modes and unterminated HS-RX mode. 
     - It supports ALP Mode for different applications with long channels 
       that enables fast lane turnaround mode to increase bandwidth of 
       communication in the reverse direction of the MIPI link. The ALP 
       mode is key to the CSI-2(R) Unified Serial Linking capability, 
       which decreases interface wires and helps to allow a more extensive 
       range.

Arasan's MIPI C-PHY(SM) v2.0 / D-PHY(SM) v2.5 combo IP is available to license 
immediately. For availability, lead time and purchase of  Test Chips (on TSMC 
FINFET) along with the HDK programmed with our CSI-2 or DSI-2 IP cores, please 
contact Arasan sales.

About Arasan

Arasan Chip Systems, a contributing member of the MIPI Association since 2005 
is a leading provider of IP for mobile storage and mobile connectivity 
interfaces with over a billion chips shipped with our MIPI IP. Arasan's 
high-quality, silicon-proven, Total IP Solutions include digital IP, AMS PHY 
IP, Verification IP, HDK and Software. Arasan has a focused product portfolio 
targeting mobile SoC's. The term Mobile has evolved over our two decade history 
to include all things mobile – starting with PDA's in the mid 90's to 
Smartphones & Tablets of the 2000's to today's Automobiles, Drones and IoT. 
Arasan is at the forefront of this evolution of "Mobile" with its 
standards-based IP at the heart of Mobile SoC's.

Over a billion chips have been shipped with Arasan IP including with all of the 
top 10 semiconductor companies.

Contact: 
Dr. Sam Beal 
Mktg1@arasan.com 

Source - Arasan Chip Systems, Inc.  
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